LL_ADC_Init and LL_ADC_DeInit APIs migration

The LL initialization and de-initialization functions previously available in the stm32tnxx_ll_adc.c files within HAL1 are no longer present in HAL2. In HAL2, all LL C files ( stm32tnxx_ll_adc.c) have been removed, leaving only the LL header files ( stm32tnxx_ll_adc.h) that contain static inline functions.

If users need to initialize or de-initialize ADC using the LL layer, they have two methods:

  • Utilize STM32CubeMX2 Code Generation: Rely on STM32CubeMX2 to generate code with the LL layer for ADC initialization and de-initialization.

  • Replace manually the initialization and de-initialization functionsReplace the LL_ADC_Init and LL_ADC_DeInit functions

    manually with equivalent sequences using the static inline functions provided in the stm32tnxx_ll_adc.h file, tailored to their specific configuration and requirements.

This approach ensures that the initialization and de-initialization sequences are precisely addressing the given use case based on the LL static inline functions provided in the stm32tnxx_ll_adc.h header file. The sequences offer improved footprint optimization compared to the previous LL initialization functions found in stm32tnxx_ll_adc.c.

Related concept: Remove stm32tnxx_ll_ppp.c files

Method 1: Utilize STM32CubeMX2 Code Generation

LL ADC configuration panel

Create a new project with the STM32CubeMX2, then start the initialization and the main configuration.

Example Image

LL ADC main features configuration

Configure the main features of the ADC

Example Image

LL ADC advanced features configuration

Configure the advanced features of the ADC if needed

Example Image

LL ADC DMA configuration

Configure the ADC DMA channels if needed

Example Image

LL ADC NVIC configuration

The NVIC configuration for ADC enables event interrupt, with each set to priority 0 and subpriority 0.

Example Image

Generated ADC initialization sequence

The ADC initialization and de-initialization sequences are generated in the mx_adc1_init and mx_adc1_deinit functions in mx_adc1.c file under $YOUR_PROJECT_NAME$/$YOUR_PROJECT_NAME$_SW/generated/STM32Cube_CodeGen.

STM32CubeMX2 Generated : ADC initialization sequence

Topic

Code Snippet HAL1

Code Snippet HAL2

Init and config sequence function 

static void MX_ADC1_Init(void)
{

    LL_ADC_CommonInitTypeDef ADC_CommonInitStruct = {0};
    LL_ADC_InitTypeDef ADC_InitStruct = {0};
    LL_ADC_REG_InitTypeDef ADC_REG_InitStruct = {0};

    LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
    LL_DMA_InitTypeDef DMA_InitStruct = {0};

    LL_RCC_SetADCDACClockSource(LL_RCC_ADCDAC_CLKSOURCE_HSI);

    /* Peripheral clock enable */
    LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC12);

    LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC);
    /**ADC1 GPIO Configuration
    PC0   ------> ADC1_IN1
    */
    GPIO_InitStruct.Pin = LL_GPIO_PIN_0;
    GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
    GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
    LL_GPIO_Init(GPIOC, &GPIO_InitStruct);

    /* ADC1 DMA Init */

    /* GPDMA1_REQUEST_ADC1 Init */
    DMA_InitStruct.SrcAddress = 0x00000000U;
    DMA_InitStruct.DestAddress = 0x00000000U;
    DMA_InitStruct.Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
    DMA_InitStruct.BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
    DMA_InitStruct.DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
    DMA_InitStruct.SrcBurstLength = 1;
    DMA_InitStruct.DestBurstLength = 1;
    DMA_InitStruct.SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
    DMA_InitStruct.DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
    DMA_InitStruct.SrcIncMode = LL_DMA_SRC_FIXED;
    DMA_InitStruct.DestIncMode = LL_DMA_DEST_FIXED;
    DMA_InitStruct.Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
    DMA_InitStruct.BlkDataLength = 0x00000000U;
    DMA_InitStruct.TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
    DMA_InitStruct.TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
    DMA_InitStruct.TriggerSelection = 0x00000000U;
    DMA_InitStruct.Request = LL_GPDMA1_REQUEST_ADC1;
    DMA_InitStruct.TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
    DMA_InitStruct.SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
    DMA_InitStruct.DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
    DMA_InitStruct.LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT1;
    DMA_InitStruct.LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
    DMA_InitStruct.LinkedListBaseAddr = 0x00000000U;
    DMA_InitStruct.LinkedListAddrOffset = 0x00000000U;
    LL_DMA_Init(GPDMA1, LL_DMA_CHANNEL_1, &DMA_InitStruct);

    /* ADC1 interrupt Init */
    NVIC_SetPriority(ADC1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
    NVIC_EnableIRQ(ADC1_IRQn);

    /** Common config
    */
    LL_ADC_SetTriggerFrequencyMode(ADC1, LL_ADC_TRIGGER_FREQ_HIGH);
    ADC_CommonInitStruct.CommonClock = LL_ADC_CLOCK_ASYNC_DIV1;
    LL_ADC_CommonInit(__LL_ADC_COMMON_INSTANCE(ADC1), &ADC_CommonInitStruct);
    ADC_InitStruct.Resolution = LL_ADC_RESOLUTION_14B;
    ADC_InitStruct.LowPowerMode = LL_ADC_LP_MODE_NONE;
    ADC_InitStruct.LeftBitShift = LL_ADC_LEFT_BIT_SHIFT_1;
    LL_ADC_Init(ADC1, &ADC_InitStruct);
    LL_ADC_SetGainCompensation(ADC1, 0);
    ADC_REG_InitStruct.SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
    ADC_REG_InitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
    ADC_REG_InitStruct.ContinuousMode = LL_ADC_REG_CONV_SINGLE;
    ADC_REG_InitStruct.Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
    ADC_REG_InitStruct.DataTransferMode = LL_ADC_REG_DR_TRANSFER;
    LL_ADC_REG_Init(ADC1, &ADC_REG_InitStruct);
    LL_ADC_SetOverSamplingScope(ADC1, LL_ADC_OVS_DISABLE);

    /* Disable ADC deep power down (enabled by default after reset state) */
    LL_ADC_DisableDeepPowerDown(ADC1);
    /* Enable ADC internal voltage regulator */
    LL_ADC_EnableInternalRegulator(ADC1);
    /* Delay for ADC internal voltage regulator stabilization. */
    /* Compute number of CPU cycles to wait for, from delay in us. */
    /* Note: Variable divided by 2 to compensate partially */
    /* CPU processing cycles (depends on compilation optimization). */
    /* Note: If system core clock frequency is below 200kHz, wait time */
    /* is only a few CPU processing cycles. */
    __IO uint32_t wait_loop_index;
    wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (100000 * 2))) / 10);
    while(wait_loop_index != 0)
    {
        wait_loop_index--;
    }
}

ADC_TypeDef *mx_adc1_init(void)
{
    LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC12);

    LL_RCC_SetADCDACClockSource(LL_RCC_ADCDAC_CLKSOURCE_PSIS);

    /****************************************************************************/
    /* Configuration of basic features (mandatory)                              */
    /****************************************************************************/

    /* ==================== ADC instance ==================== */
    /* LL_ADC_SetResolution(ADC1, LL_ADC_RESOLUTION_12B); */
    /* LL_ADC_SetSamplingMode(ADC1, LL_ADC_SAMPLING_MODE_NORMAL); */

    /* ==================== Group Regular ==================== */
    /* LL_ADC_REG_SetContinuousMode(ADC1, LL_ADC_REG_CONV_SINGLE); */
    /* LL_ADC_REG_SetTriggerSource(ADC1, LL_ADC_REG_TRIG_SOFTWARE); */

    /* LL_ADC_REG_SetSequencerDiscont(ADC1, LL_ADC_REG_SEQ_DISCONT_DISABLE); */
    LL_ADC_REG_SetOverrun(ADC1, LL_ADC_REG_OVR_DATA_OVERWRITTEN);

    /* The sequencer is currently empty, please add a channel in STM32CubeMX2 interface */
    /* LL_ADC_REG_SetSequencerLength(ADC1, LL_ADC_REG_SEQ_SCAN_DISABLE); */
    /* Section commented due to information missing in STM32CubeMX2 interface
    LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_1, ...);
    LL_ADC_SetChannelSamplingTime(ADC1, ..., ...);
    */

    /****************************************************************************/
    /* Configuration of additional features (optional)                          */
    /****************************************************************************/
    LL_ADC_SetLeftBitShift(ADC1, LL_ADC_LEFT_BIT_SHIFT_1);
    LL_ADC_SetGainCompensation(ADC1, 1000);

    LL_ADC_SetLowPowerMode(ADC1, LL_ADC_LP_AUTOWAIT);

    LL_ADC_SetAnalogWDScope(ADC1, LL_ADC_AWD_1, LL_ADC_GROUP_REGULAR, LL_ADC_CHANNEL_0);
    LL_ADC_SetAnalogWDThresholds(ADC1, LL_ADC_AWD_1,LL_ADC_AWD_THRESHOLD_HIGH,4194303);
    LL_ADC_SetAnalogWDThresholds(ADC1, LL_ADC_AWD_1,LL_ADC_AWD_THRESHOLD_LOW,0);
    LL_ADC_SetAnalogWDFiltering(ADC1, LL_ADC_AWD_1, LL_ADC_AWD_FILTERING_NONE);

    /* LL_ADC_SetOverSamplingScope(ADC1, LL_ADC_OVS_DISABLE); */
    /* LL_ADC_SetOverSamplingDiscont(ADC1, LL_ADC_OVS_CONT); */
    LL_ADC_ConfigOverSamplingRatioShift(ADC1, 1, LL_ADC_OVS_SHIFT_RIGHT_1);

    LL_ADC_SetOffsetChannel(ADC1, LL_ADC_OFFSET_1, LL_ADC_CHANNEL_0);
    LL_ADC_SetOffsetLevel(ADC1, LL_ADC_OFFSET_1, 4194303);
    LL_ADC_SetOffsetSignedSaturation(ADC1, LL_ADC_OFFSET_1, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
    LL_ADC_SetOffsetUnsignedSaturation(ADC1, LL_ADC_OFFSET_1, LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE);

    /* GPIO Clocks activation */
    LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);

    /**
        ADC1 GPIO Configuration

        [GPIO Pin] ------> [Signal Name]

        PA0     ------>   ADC1_IN0
        **/

    /* Activate the Pull-up, Pull-down resistor, or No pull for the current IO */
    LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_0, LL_GPIO_PULL_NO);

    /* Configure IO direction mode (Input, Output, Alternate or Analog) */
    LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_ANALOG);

    /* Enable the interruption for ADC */
    NVIC_SetPriority(ADC1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
    NVIC_EnableIRQ(ADC1_IRQn);
    /* Configure DMA */

    /* ################################################## ADC1_GLOBAL DMA configuration */
    /* Enable LPDMA1 clock */

    LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_LPDMA1);

    /* Configure DMA channel transfer request */
    LL_DMA_SetPeriphRequest(LPDMA1_CH0, LL_LPDMA1_REQUEST_ADC1);

    /* Configure DMA channel transfer direction */
    LL_DMA_SetDataTransferDirection(LPDMA1_CH0, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);

    /* Configure DMA channel priority level */
    LL_DMA_SetChannelPriorityLevel(LPDMA1_CH0, LL_DMA_PRIORITY_LOW_WEIGHT_LOW);

    /* Configure DMA channel transfer register 1 */
    LL_DMA_ConfigTransfer(LPDMA1_CH0,
                            (LL_DMA_SRC_ADDR_FIXED | LL_DMA_SRC_DATA_WIDTH_WORD |
                            LL_DMA_DEST_ADDR_INCREMENTED | LL_DMA_DEST_DATA_WIDTH_WORD));

    /* Enable the interruption for DMA */
    NVIC_SetPriority(LPDMA1_CH0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
    NVIC_EnableIRQ(LPDMA1_CH0_IRQn);

    return ADC1;
}

Deinit sequence function 

void MX_ADC_DeInit(void)
{
  if (LL_ADC_DeInit(ADC1) != HAL_OK)
  {
    Error_Handler();
  }
}

void mx_adc1_deinit(void)
{
    LL_ADC_Disable(ADC1);

    LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC12);

    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC12);
    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC12);

    NVIC_DisableIRQ(ADC1_IRQn);
    /* ### GPIO deinitialization of ADC1: ADC1_IN0 ########################### */

    /* Configure IO in Analog Mode */
    LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_ANALOG);

    /* Configure the default Alternate Function in current IO */
    LL_GPIO_SetAFPin_0_7(GPIOA, LL_GPIO_PIN_0, LL_GPIO_AF_0);

    /* Configure the default value for IO Speed */
    LL_GPIO_SetPinSpeed(GPIOA, LL_GPIO_PIN_0, LL_GPIO_SPEED_FREQ_LOW);

    /* Configure the default value IO Output Type */
    LL_GPIO_SetPinOutputType(GPIOA, LL_GPIO_PIN_0, LL_GPIO_OUTPUT_PUSHPULL);

    /* Deactivate the Pull-up and Pull-down resistor for the current IO */
    LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_0, LL_GPIO_PULL_NO);

    /* Reset the IO output state */
    LL_GPIO_WriteOutputPin(GPIOA, LL_GPIO_PIN_0, LL_GPIO_PIN_RESET);

    /* Configure DMA */
    /* De-initialize the DMA channel */
    LL_DMA_DisableChannel(LPDMA1_CH0);
    LL_DMA_ClearFlag(LPDMA1_CH0, LL_DMA_FLAG_ALL);

    LL_DMA_WRITE_REG(LPDMA1_CH0, CCR, 0U);
    LL_DMA_WRITE_REG(LPDMA1_CH0, CTR1, 0U);
    LL_DMA_WRITE_REG(LPDMA1_CH0, CTR2, 0U);
    LL_DMA_WRITE_REG(LPDMA1_CH0, CBR1, 0U);
    LL_DMA_WRITE_REG(LPDMA1_CH0, CLLR, 0U);

    /* Disable the interruption for DMA */
    NVIC_DisableIRQ(LPDMA1_CH0_IRQn);
}

Method 2: Replace manually the initialization and de-initialization functions

LL_ADC_Init() API migration

According to the use case, implement the precise sequence of calls based on the LL static inline functions provided in the stm32tnxx_ll_adc.h header file.

ADC Mode Comparison between HAL1 and HAL2

HAL1

HAL2 

LL_ADC_InitTypeDef adc_InitStruct;

adc_InitStruct.LowPowerMode  = LL_ADC_LP_MODE_NONE;
adc_InitStruct.Resolution    = LL_ADC_RESOLUTION_12B;
adc_InitStruct.DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
LL_ADC_Init(ADC1, &adc_InitStruct);

LL_ADC_SetLowPowerMode(ADC1, LL_ADC_LP_MODE_NONE);
LL_ADC_SetResolution(ADC1, LL_ADC_RESOLUTION_12B);
LL_ADC_SetDataAlignment(ADC1, LL_ADC_DATA_ALIGN_RIGHT);

LL_ADC_CommonInit() API migration

ADC Mode Comparison between HAL1 and HAL2

HAL1

HAL2

Case of Multimode supported and ADC configured for LL_ADC_MULTI_INDEPENDENT 

LL_ADC_CommonInitTypeDef adc_CommonInitStruct;
adc_CommonInitStruct.CommonClock           = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
adc_CommonInitStruct.Multimode             = LL_ADC_MULTI_INDEPENDENT;
adc_CommonInitStruct.MultiDMATransfer      = LL_ADC_MULTI_REG_DMA_EACH_ADC;
adc_CommonInitStruct.MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
LL_ADC_CommonInit(ADC1_COMMON, &adc_CommonInitStruct);

LL_ADC_SetCommonClock(ADC1_COMMON, LL_ADC_CLOCK_ASYNC_DIV2);
LL_ADC_SetMultimode(ADC1_COMMON, LL_ADC_MULTI_INDEPENDENT);
LL_ADC_SetMultiDMATransfer(ADC1_COMMON, LL_ADC_MULTI_REG_DMA_RES_32_16B);
LL_ADC_SetMultiTwoSamplingDelay(ADC1_COMMON, LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES);

Case of Multimode supported and ADC configured for LL_ADC_MULTI_DUAL_REG_SIMULT 

LL_ADC_CommonInitTypeDef adc_CommonInitStruct;
adc_CommonInitStruct.CommonClock           = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
adc_CommonInitStruct.Multimode             = LL_ADC_MULTI_DUAL_REG_SIMULT;
adc_CommonInitStruct.MultiDMATransfer      = LL_ADC_MULTI_REG_DMA_EACH_ADC;
adc_CommonInitStruct.MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
LL_ADC_CommonInit(ADC1_COMMON, &adc_CommonInitStruct);

LL_ADC_SetCommonClock(ADC1_COMMON, LL_ADC_CLOCK_ASYNC_DIV2);
LL_ADC_SetMultimode(ADC1_COMMON, LL_ADC_MULTI_DUAL_REG_SIMULT);
LL_ADC_SetMultiDMATransfer(ADC1_COMMON, LL_ADC_MULTI_REG_DMA_RES_32_16B);
LL_ADC_SetMultiTwoSamplingDelay(ADC1_COMMON, LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES);

Case of Multimode not supported 

LL_ADC_CommonInitTypeDef adc_CommonInitStruct;
adc_CommonInitStruct.CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
LL_ADC_CommonInit(ADC1_COMMON, &adc_CommonInitStruct);

LL_ADC_SetCommonClock(ADC1_COMMON, LL_ADC_CLOCK_ASYNC_DIV2);

LL_ADC_REG_Init() API migration

ADC Mode Comparison between HAL1 and HAL2

HAL1

HAL2

Case of SequencerLength configured for SCAN DISABLE 

LL_ADC_REG_InitTypeDef adc_RegInitStruct;
adc_RegInitStruct.TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
adc_RegInitStruct.SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;
adc_RegInitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
adc_RegInitStruct.ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
adc_RegInitStruct.DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;
adc_RegInitStruct.Overrun          = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
LL_ADC_REG_Init(ADC1, &adc_RegInitStruct);

LL_ADC_REG_SetSequencerLength(ADC1, LL_ADC_REG_SEQ_SCAN_DISABLE);
LL_ADC_REG_SetTriggerSource(ADC1, LL_ADC_REG_TRIG_SOFTWARE);
LL_ADC_REG_SetSequencerDiscont(ADC1, LL_ADC_REG_SEQ_DISCONT_DISABLE);
LL_ADC_REG_SetContinuousMode(ADC1, LL_ADC_REG_CONV_SINGLE);
LL_ADC_REG_SetDMATransfer(ADC1, LL_ADC_REG_DMA_TRANSFER_NONE);
LL_ADC_REG_SetOverrun(ADC1, LL_ADC_REG_OVR_DATA_OVERWRITTEN);

Case of SequencerLength configured for SCAN ENABLE 

LL_ADC_REG_InitTypeDef adc_RegInitStruct;
adc_RegInitStruct.TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
adc_RegInitStruct.SequencerLength  = LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS;
adc_RegInitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_1RANK;
adc_RegInitStruct.ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
adc_RegInitStruct.DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;
adc_RegInitStruct.Overrun          = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
LL_ADC_REG_Init(ADC1, &adc_RegInitStruct);

LL_ADC_REG_SetSequencerLength(ADC1, LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS);
LL_ADC_REG_SetTriggerSource(ADC1, LL_ADC_REG_TRIG_SOFTWARE);
LL_ADC_REG_SetSequencerDiscont(ADC1, LL_ADC_REG_SEQ_DISCONT_1RANK);
LL_ADC_REG_SetContinuousMode(ADC1, LL_ADC_REG_CONV_SINGLE);
LL_ADC_REG_SetDMATransfer(ADC1, LL_ADC_REG_DMA_TRANSFER_NONE);
LL_ADC_REG_SetOverrun(ADC1, LL_ADC_REG_OVR_DATA_OVERWRITTEN);

LL_ADC_INJ_Init() API migration

ADC Mode Comparison between HAL1 and HAL2

HAL1

HAL2

Case of SequencerLength configured for SCAN DISABLE 

LL_ADC_INJ_InitTypeDef adc_InjInitStruct;
adc_InjInitStruct.TriggerSource    = LL_ADC_INJ_TRIG_SOFTWARE;
adc_InjInitStruct.SequencerLength  = LL_ADC_INJ_SEQ_SCAN_DISABLE;
adc_InjInitStruct.SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
adc_InjInitStruct.TrigAuto         = LL_ADC_INJ_TRIG_INDEPENDENT;
LL_ADC_INJ_Init(ADC1, &adc_InjInitStruct);

LL_ADC_INJ_SetSequencerDiscont(ADC1, LL_ADC_INJ_SEQ_DISCONT_DISABLE);
LL_ADC_INJ_SetTrigAuto(ADC1, LL_ADC_INJ_TRIG_INDEPENDENT);
LL_ADC_INJ_SetTriggerSource(ADC1, LL_ADC_INJ_TRIG_SOFTWARE);
LL_ADC_INJ_SetSequencerLength(ADC1, LL_ADC_REG_SEQ_SCAN_DISABLE);

Case of SequencerLength configured for SCAN ENABLE 

LL_ADC_INJ_InitTypeDef adc_InjInitStruct;
adc_InjInitStruct.TriggerSource    = LL_ADC_INJ_TRIG_SOFTWARE;
adc_InjInitStruct.SequencerLength  = LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS;
adc_InjInitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_1RANK;
adc_InjInitStruct.TrigAuto         = LL_ADC_INJ_TRIG_INDEPENDENT;
LL_ADC_INJ_Init(ADC1, &adc_InjInitStruct);

LL_ADC_INJ_SetSequencerDiscont(ADC1, LL_ADC_INJ_SEQ_DISCONT_1RANK);
LL_ADC_INJ_SetTrigAuto(ADC1, LL_ADC_INJ_TRIG_INDEPENDENT);
LL_ADC_INJ_SetTriggerSource(ADC1, LL_ADC_INJ_TRIG_SOFTWARE);
LL_ADC_INJ_SetSequencerLength(ADC1, LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS);

LL_ADC_DeInit() API migration

Comparison of HAL1 and HAL2

HAL1

HAL2 

LL_ADC_DeInit(ADC1)

 /* case of ADC group regular */
LL_ADC_REG_StopConversion(ADC1);

/* case of ADC group injected */
LL_ADC_INJ_StopConversion(ADC1);

LL_ADC_INJ_SetQueueMode(ADC1, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);

LL_ADC_Disable(ADC1);

LL_ADC_INJ_IsStopConversionOngoing(ADC1);
LL_ADC_INJ_IsConversionOngoing(ADC1);

LL_ADC_REG_IsStopConversionOngoing(ADC1):
LL_ADC_REG_IsConversionOngoing(ADC1);

LL_ADC_IsDisableOngoing(ADC1);
LL_ADC_IsEnabled(ADC1);

LL_ADC_DisableIT_ADRDY(ADC1);
LL_ADC_DisableIT_EOC(ADC1);
LL_ADC_DisableIT_EOS(ADC1);
LL_ADC_DisableIT_OVR(ADC1);
LL_ADC_DisableIT_EOSMP(ADC1);
LL_ADC_DisableIT_AWD1(ADC1);
LL_ADC_DisableIT_AWD2(ADC1);
LL_ADC_DisableIT_AWD3(ADC1);
LL_ADC_DisableIT_JEOC(ADC1);
LL_ADC_DisableIT_JEOS(ADC1);
LL_ADC_DisableIT_JQOVF(ADC1);

LL_ADC_ClearFlag_ADRDY(ADC1);
LL_ADC_ClearFlag_EOC(ADC1);
LL_ADC_ClearFlag_EOS(ADC1);
LL_ADC_ClearFlag_OVR(ADC1);
LL_ADC_ClearFlag_EOSMP(ADC1);
LL_ADC_ClearFlag_AWD1(ADC1);
LL_ADC_ClearFlag_AWD2(ADC1);
LL_ADC_ClearFlag_AWD3(ADC1);
LL_ADC_ClearFlag_JEOC(ADC1);
LL_ADC_ClearFlag_JEOS(ADC1);
LL_ADC_ClearFlag_JQOVF(ADC1);

LL_ADC_DisableInternalRegulator(ADC1);
CLEAR_BIT(ADC_CR_ADCALDIF);
LL_ADC_EnableDeepPowerDown(ADC1);
LL_ADC_IsAnalogWDChannelMonitored(ADC1, LL_ADC_AWD1, LL_ADC_CHANNEL_1);
LL_ADC_SetAnalogWDScope(ADC1, LL_ADC_AWD1, L_ADC_GROUP_REGULAR, LL_ADC_CHANNEL_1);
LL_ADC_INJ_SetSequencerDiscont(ADC1, LL_ADC_INJ_SEQ_DISCONT_DISABLE);

LL_ADC_SetLowPowerMode(ADC1, LL_ADC_LP_MODE_NONE);
LL_ADC_REG_SetTriggerSource(ADC1, LL_ADC_REG_TRIG_SOFTWARE);

LL_ADC_SetResolution(ADC4, LL_ADC_RESOLUTION_12B);
LL_ADC_INJ_SetTrigAuto(ADC1, LL_ADC_INJ_TRIG_INDEPENDENT);
LL_ADC_REG_SetSequencerDiscont(ADC1, LL_ADC_REG_SEQ_DISCONT_DISABLE);
LL_ADC_REG_SetContinuousMode(ADC1, LL_ADC_REG_CONV_SINGLE);
LL_ADC_REG_SetOverrun(ADC1, LL_ADC_REG_OVR_DATA_OVERWRITTEN);
LL_ADC_SetDataAlignment(ADC1, LL_ADC_DATA_ALIGN_RIGHT);
LL_ADC_REG_SetDMATransfer(ADC1, LL_ADC_REG_DMA_TRANSFER_NONE);
LL_ADC_REG_StopSamplingPhase(ADC1).
CLEAR_BIT(ADC1->SMPR1,(ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4| ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1));
LL_ADC_ConfigAnalogWDThresholds(ADC1, LL_ADC_AWD1,
                                            0xFFF,
                                            0xFFF);
LL_ADC_REG_SetSequencerLength(ADC1, LL_ADC_INJ_SEQ_SCAN_DISABLE);
LL_ADC_SetAWDFilteringConfiguration(ADC1, LL_ADC_AWD1, LL_ADC_AWD_FILTERING_NONE);
LL_ADC_ConfigAnalogWDThresholds(ADC1, LL_ADC_AWD1,
                                             0U,
                                             0U);
LL_ADC_SetAWDFilteringConfiguration(ADC1, LL_ADC_AWD2, LL_ADC_AWD_FILTERING_NONE);
LL_ADC_ConfigAnalogWDThresholds(ADC1, LL_ADC_AWD2,
                                             0U,
                                             0U);
LL_ADC_SetAWDFilteringConfiguration(ADC1, LL_ADC_AWD3, LL_ADC_AWD_FILTERING_NONE);
LL_ADC_ConfigAnalogWDThresholds(ADC1, LL_ADC_AWD3,
                                             0U,
                                             0U);
CLEAR_BIT(ADC1->SQR1,(ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2| ADC_SQR1_SQ1 | ADC_SQR1_L) );

CLEAR_BIT(ADC1->SQR2,(ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7| ADC_SQR2_SQ6 | ADC_SQR2_SQ5));

CLEAR_BIT(ADC1->SQR3,(ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10));
CLEAR_BIT(ADC1->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
LL_ADC_SetOffset(ADC1, LL_ADC_OFFSET_1, LL_ADC_CHANNEL_1, 0x00000000);
LL_ADC_SetOffsetChannel(ADC1, LL_ADC_OFFSET_1, LL_ADC_CHANNEL_1);
LL_ADC_SetOffset(ADC1, LL_ADC_OFFSET_2, LL_ADC_CHANNEL_1, 0x00000000);
LL_ADC_SetOffsetChannel(ADC1, LL_ADC_OFFSET_2, LL_ADC_CHANNEL_1);
LL_ADC_SetOffset(ADC1, LL_ADC_OFFSET_3, LL_ADC_CHANNEL_1, 0x00000000);
LL_ADC_SetOffsetChannel(ADC1, LL_ADC_OFFSET_3, LL_ADC_CHANNEL_1);
LL_ADC_SetOffset(ADC1, LL_ADC_OFFSET_4, LL_ADC_CHANNEL_1, 0x00000000);
LL_ADC_SetOffsetChannel(ADC1, LL_ADC_OFFSET_4, LL_ADC_CHANNEL_1);
LL_ADC_SetAnalogWDScope(ADC1, LL_ADC_AWD1, LL_ADC_GROUP_NONE, LL_ADC_CHANNEL_1);
LL_ADC_SetAnalogWDScope(ADC1, LL_ADC_AWD2, LL_ADC_GROUP_NONE, LL_ADC_CHANNEL_1);
LL_ADC_SetAnalogWDScope(ADC1, LL_ADC_AWD3, LL_ADC_GROUP_NONE, LL_ADC_CHANNEL_1);
LL_ADC_SetChannelSingleDiff(ADC1, LL_ADC_CHANNEL_1, LL_ADC_SINGLE_ENDED);
LL_ADC_SetCalibrationOffsetFactor(ADC1, 0x00);

LL_ADC_(Set/Get)AnalogWDMonitChannels() API migration

Comparison of HAL1 and HAL2

HAL1

HAL2 

LL_ADC_SetAnalogWDMonitChannels(ADC1 , AWD1 , LL_ADC_AWD_DISABLE);
LL_ADC_SetAnalogWDMonitChannels(ADC1 , AWD1 , LL_ADC_AWD_CHANNEL_0_REG);
LL_ADC_SetAnalogWDMonitChannels(ADC1 , AWD1 , LL_ADC_AWD_CHANNEL_0_INJ);
LL_ADC_SetAnalogWDMonitChannels(ADC1 , AWD1 , LL_ADC_AWD_CHANNEL_0_REG_INJ);
...
LL_ADC_SetAnalogWDMonitChannels(ADC1 , AWD1 , LL_ADC_AWD_CHANNEL_XX_REG);
LL_ADC_SetAnalogWDMonitChannels(ADC1 , AWD1 , LL_ADC_AWD_CHANNEL_XX_INJ);
LL_ADC_SetAnalogWDMonitChannels(ADC1 , AWD1 , LL_ADC_AWD_CHANNEL_XX_REG_INJ);

LL_ADC_GetAnalogWDMonitChannels(ADC1 , AWD1);

LL_ADC_SetAnalogWDScope(ADC1 , AWD1 , LL_ADC_GROUP_NONE ,LL_ADC_CHANNEL_NONE);
LL_ADC_SetAnalogWDScope(ADC1 , AWD1 , LL_ADC_GROUP_REGULAR ,LL_ADC_CHANNEL_0);
LL_ADC_SetAnalogWDScope(ADC1 , AWD1 , LL_ADC_GROUP_INJECTED ,LL_ADC_CHANNEL_0);
LL_ADC_SetAnalogWDScope(ADC1 , AWD1 , LL_ADC_GROUP_REGULAR_INJECTED ,LL_ADC_CHANNEL_0);
...
LL_ADC_SetAnalogWDScope(ADC1 , AWD1 , LL_ADC_GROUP_REGULAR ,LL_ADC_CHANNEL_XX);
LL_ADC_SetAnalogWDScope(ADC1 , AWD1 , LL_ADC_GROUP_INJECTED ,LL_ADC_CHANNEL_XX);
LL_ADC_SetAnalogWDScope(ADC1 , AWD1 , LL_ADC_GROUP_REGULAR_INJECTED ,LL_ADC_CHANNEL_XX);

LL_ADC_GetAnalogWDScopeGroup(ADC1 , AWD1);

LL_ADC_CommonDeInit() API migration

According to the used ADC1, implement the precise calls to LL_AHB2_GRP1_ForceReset() and LL_AHB2_GRP1_ReleaseReset().

Comparison of HAL1 and HAL2

HAL1

HAL2 

LL_ADC_CommonDeInit(ADC1);

LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC);
LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC);